1. Field of the Invention
The present invention relates to a chip package, and more particularly to a chip package with an embedded panel-shaped component.
2. Description of the Related Art
With the advance of electronic technology, electronic devices have developed to have higher processing speed, multiple functions, high integration, miniaturized dimension, and low price. Following that trend, chip package technology also develops toward miniaturization and high integration. In the conventional ball grid array (BGA) package technology, a package substrate is used as a carrier for an integrated circuit (IC) chip. Then, the chip is electrically connected to the top surface of the package substrate by flip-chip bonding or wire bonding. A plurality of solder balls are disposed on the bottom surface of the package substrate in area arrays. Accordingly, the chip is electrically connected to an electronic apparatus in the next level, such as a printed circuit board, through the internal circuit of the package substrate and the solder balls on the bottom surface.
However, in the conventional BGA package technology, a package substrate with a high layout density is used, accompanied with the flip-chip bonding method or the wire bonding method, the signal transmission route would be too long. In solution, a bumpless build-up layer (BBUL) chip package method has been developed, wherein the flip-chip bonding process or the wire bonding process is omitted, and a multi-layered interconnection structure is directly formed on the chip. The multi-layered interconnection structure is electrically connected to an electronic apparatus in the next level by forming electrical connection points on the structure, such as solder balls or pins in area arrays.
FIG. 1 is a schematic cross-sectional view of a conventional BBUL chip package. Referring to FIG. 1, the BBUL chip package 100 comprises a stiffener 110, a chip 120, an interconnection structure 130, an encapsulant 140, and a plurality of solder balls 150. Wherein, the stiffener 110 has an opening 110a, and the chip 120 is disposed in the opening 110a. In addition, the encapsulant 140 is disposed between the chip 120 and the inside wall of the opening 10a. The chip 120 has a plurality of pads 122 on the active surface, and the interconnection structure 130 is disposed on the active surface of the chip 120, and electrically coupled to the pads 122.
In detail, the interconnection structure 130 comprises a plurality of dielectric layers 132, a plurality of circuit layers 134 and a plurality of conductive vias 134a. Wherein, the circuit layers 134 are sequentially stacked on the chip 120 and the stiffener 110. One of the circuit layers 134, which is the closest to the chip 120, is electrically coupled to the pads 122 of the chip 120 through the conductive vias 134a. In addition, the dielectric layers 132 are disposed between every two neighboring circuit layers 134. Each of the conductive vias passes through one the dielectric layers 132, and electrically connects at least two circuit layers 134. The conventional BBUL chip package 100 may further comprise a plurality of pads 160 and a solder mask layer 170. Wherein, the pads 160 are disposed on the interconnection structure 130. The solder mask layer 170 is disposed on the interconnection structure 130 to expose the pads 160. The solder balls 150 are disposed over the pads 160.
Accordingly, though the conventional BBUL chip package 100 has better reliability and electrical performance, the crosstalk problem of the high-frequency signals becomes serious due to narrowed line pitches and increased layout density. In other words, the electrical performance of the conventional BBUL chip package 100 will be affected because of narrowed line pitches and increased layout density.